The present invention relates to a latch circuit for transmitting a pulse signal, a shift register circuit having this latch circuit and an image display device employing this shift register circuit.
Herein is provided a description for a conventional liquid crystal display device and a shift register circuit that constitutes the data signal line drive circuit and scanning signal line drive circuit of the device, which are taken as examples of an image display device and a shift register circuit having the conventional latch circuit. It is to be noted that the shift register and the image display device of the present invention are limited neither to the above liquid crystal display device nor to the shift register for the liquid crystal display device and is able to be applied to an image display device and a shift register for the image display device of another type.
Conventionally, as the above liquid crystal display device, there has been known a liquid crystal display device of an active matrix driving system. As shown in FIG. 37, this liquid crystal display device is constructed of a pixel array ARY, a scanning signal line drive circuit GD and a data signal line drive circuit SD. In the above pixel array ARY, pixels PIX are arranged in the vicinity of intersections of a number of scanning signal lines GL and a number of data signal lines SL that intersect each other and connected to the adjacent scanning signal line GL and data signal line SL so as to be arranged in a matrix form.
The data signal line drive circuit SD samples an input video signal dat in synchronization with a timing signal such as a clock signal cks and writes the resulting data into the data signal lines SL while amplifying the signal as the occasion demands. The scanning signal line drive circuit GD successively selects the scanning signal lines GL in synchronization with a timing signal such as a clock signal ckg, writes the video signal (data) dat written in the data signal lines SL into the corresponding pixels PIX by controlling the opening and closing of switching elements existing in the pixels PIX and holds the data written in the pixels PIX.
As shown in FIG. 38, each pixel PIX is constructed of a field-effect transistor SW that serves as the aforementioned switching element and a pixel capacity comprised of a liquid crystal capacity CL and an auxiliary capacity (added as the occasion demands) CS. Then, the data signal line SL and one electrode of the pixel capacity are connected to each other via the drain and source of the transistor SW, while the gate of the transistor SW is connected to the scanning signal line GL. Further, the other electrode of the pixel capacity is connected to a common electrode (not shown) common to all the pixels. In the above construction, the transmittance or reflectance of the liquid crystals is modulated by a voltage applied to the liquid crystal capacity CL, thereby driving the pixel for display.
A method for writing the aforementioned video signal dat into the data signal lines SL will be described next. As a system for driving the data signal lines SL, there are existing a dot sequence driving system and a line sequence driving system, and reference is herein made to the dot sequence driving system. FIG. 39 shows a detailed circuit diagram of the data signal line drive circuit SD. The video signal dat inputted to a video signal line DAT is written into the data signal line SL by opening and closing a sampling circuit AS by means of an output pulse of each stage of a shift register circuit 1 synchronized with this video signal dat.
Describing the above more concretely, a signal of a sequence of output signals n of adjacent latch circuits SR constituting the shift register circuit 1 is amplified by a buffer circuit constructed of a plurality of inverter circuits, and an inversion signal is generated as the occasion demands to output a sampling signal s and its inverted signal /s to the sampling circuit (analog switch) AS. Then, the sampling circuit AS executes switching based on the sampling signals s and /s to supply the video data from the video signal line DAT to the data signal line SL. The clock signals cks and /cks to the latch circuits SR, output signals n1 through n3 of the latch circuits SR and sampling signals s1 and s2 in the above case are shown in FIGS. 40A through 40G.
FIG. 41 shows a detailed circuit construction of the scanning signal line drive circuit GD. In this scanning signal line drive circuit GD, the signal of the sequence of the output signals n of adjacent latch circuits SR that constitutes a shift register circuit 2 is obtained by NAND circuits, and by further taking an overlap with an external pulse width control signal gps, the desired pulse width is obtained. The clock signals ckg and /ckg to the latch circuits SR, the output signals n1 through n3 of the latch circuits SR, the pulse width control signal gps and scanning signals g11 and g12 to the scanning signal lines GL in the above case are shown in FIGS. 42A through 42H.
In this case, each latch circuit SR that constitutes the shift register circuits 1 and 2 in the data signal line drive circuit SD and the scanning signal line drive circuit GD has a construction as shown in FIG. 43. It is to be noted that FIG. 43 is an example of the latch circuit SR for constituting the shift register circuits 1 and 2 that can execute scanning only in one direction. In this case, a concrete construction example of a clocked inverter circuit 3 employed in the latch circuit SR is shown in FIG. 44. By contrast, when constituting a shift register circuit that can execute bidirectional scanning, a latch circuit SR as shown in FIG. 45 is employed. Either of these latch circuits SR is a half latch circuit, which latches the input signal with either one of the leading edge or the trailing edge of the clocks ck and /ck, outputs the output signal n of a pulse width of one cycle of the clocks ck and /ck.
In order to achieve the compacting, higher resolution, reduction in mounting cost and so on of liquid crystal display devices, a technique for integrally forming the pixel array ARY and the signal line drive circuits SD and GD, which manage the display, on an identical substrate is attracting a great deal of attention. In such a drive circuit integrated type liquid crystal display device, a transparent substrate must be employed as a substrate when constituting a transmission type liquid crystal display devices that are currently widely used. In the above case, it is often the case where a polysilicon thin-film transistor that can be formed on a quartz substrate or a glass substrate as an active element such as a transistor constituting the transistor SW of the pixel PIX or the clocked inverter circuit 3.
However, the aforementioned conventional liquid crystal display device has the problems as follows. That is, as shown in FIG. 39, the data signal line drive circuit SD obtains the sampling signals s and /s on the basis of the signal of the sequence of the output signals n of adjacent two latch circuits SR. Therefore, as shown in FIGS. 40A through 40G, the trailing edge of the sampling signal s1 corresponding to the adjacent data signal line SL1 and the leading edge of the sampling signal s2 corresponding to the adjacent data signal line SL2 roughly coincide with each other.
Therefore, if the waveforms of the sampling signals s and /s become dull or a slight deviation occurs in terms of timing between output signals n from adjacent two latch circuits SR as a consequence of a characteristic change of the transistors that constitutes, for example, the data signal line drive circuit SD, then there is the possibility of the occurrence of overlap between the sampling signals s1 and s2 corresponding to the adjacent data signal lines SL1 and SL2. In such a case, a noise is imposed on the data signal line SL, leading to a concern about the occurrence of troubles such as blur, ghost and crosstalk of the display image.
In the aforementioned conventional liquid crystal display device, the clock signals cks and ckg and start signals sps and spg and so on inputted to the shift register circuits 1 and 2 are externally directly inputted as signals of the same amplitudes as those of the power voltages of the drive circuits SD and GD, as exemplified by the clock signals cks and ckg shown in FIGS. 40A through 40G and FIGS. 42A through 42H. By contrast, in the drive circuit integrated type liquid crystal display device employing the polysilicon thin-film transistors, the transistor characteristics are inferior to those of the monocrystal silicon transistor, and in particular, the threshold voltage has a high absolute value of 1 V to 6 V. Therefore, the drive power voltage cannot help being increased up to 15 to 20 V. Therefore, in the case of the drive circuit integrated type liquid crystal display device, the clock signals cks and ckg and the start signals sps and spg and so on, which are externally directly inputted, are required to have an increased amplitude.
However, if the clock signals cks and ckg have an increased amplitude, then there occurs the problem that the consumption of power increases in the external circuits such as a control circuit (not shown) for generating the clock signal and the like. Furthermore, unwanted emission from the signal lines becomes a serious problem.
In order to solve the problem due to the increase in amplitude of the clock signals cks and ckg and so on as described above, it is proposed to mount a level shifter circuit (signal boost circuit) on the signal line drive circuits SD and GD side of the liquid crystal display device, thereby reducing the voltages of the input/output interfaces.
FIG. 46 shows the data signal line drive circuit SD mounted with the above level shifter circuit. In the data signal line drive circuit SD shown in FIG. 46, a level shifter circuit LS is arranged immediately before the shift register circuit 5. Then, the inputted clock signal cks and start signal sps are supplied to the shift register circuit 5 with their amplitude (5 V) boosted to 15 V. Thus, the operating voltage of 15 V is obtained with the input voltage of 5 V. However, when the polysilicon thin-film transistor is employed in this construction, the duty ratio of the boosted signal largely varies to cause a variation in terms of timing and amplitude of the output pulse n of the data signal line drive circuit SD due to its characteristic variation, and this may incur a reduction in image quality as a consequence of the superimposition of noises on the data signal line SL. Furthermore, since the driving capability of the level shifter circuit LS itself is low, there is necessitated a buffer for driving the subsequent signal lines, also causing the problem that the consumption of power increases.
FIG. 47 shows the scanning signal line drive circuit GD mounted with the aforementioned level shifter circuit. In the scanning signal line drive circuit GD shown in FIG. 47, the level shifter circuit LS is arranged immediately before the shift register circuit 6 and on a pulse width control signal line GPS. Then, the inputted clock signal ckg, start signal spg and pulse width control signal gps are supplied to the shift register circuit 6 or a NOR circuit with their amplitude (5 V) boosted to 15 V. Also in this case, there are the concern about a reduction in image quality and the problem of an increase in consumption of power, similar to the case of the data signal line drive circuit SD mounted with the level shifter circuit LS.
FIG. 48 and FIG. 49 are concrete circuit diagrams of the aforementioned level shifter circuit LS. In the figures, the reference numerals M1 and M2 denote p-type transistors, while the reference numerals M3 through M6 denote n-type transistors. FIG. 50 shows the waveforms of input signals in and /in and output signals out and /out of the level shifter circuit LS shown in FIG. 48 or FIG. 49.
As a method for removing the concern about the reduction in image quality and the problem of the increase in consumption of power, there is a method for providing each of the shift register circuits that constitute the signal line drive circuits SD and GD with a boosting function. According to this method, by virtue of the provision of the boosting function in the latch circuit of each stage that constitutes the shift register circuit, there is no need for a signal line driving use buffer for driving the signal lines between individual latch circuits. Furthermore, since the outputs of the individual latch circuits are directly boosted instead of boosting the control signals such as the clock signal and the start signal which are inputted to the latch circuits, there can be obtained output pulse signals such as the sampling signals s and /s that are stable with respect to the characteristic variation of the transistors.
Note that, in the aforementioned level shifter circuit LS, the transistors into which the clock signals in and /in are inputted are required to have a high driving power because of the structures shown in FIG. 48 and FIG. 49. This causes another problem that the transistors have an increased gate area and the consequent increase in load and consumption of power of the clock signal line.
Accordingly, the object of the present invention is to provide a shift register circuit of which the load of the clock signal line and the consumption of power are reduced to concurrently achieve a low-voltage interface and a low consumption of power with a boosting function incorporated in the latch circuit as well as an image display device that employs this shift register circuit and concurrently has a low consumption of power and a high display quality.
In order to achieve the aforementioned object, there is provided a latch circuit which receives a pulse signal and a clock signal as inputs and transmits the pulse signal in synchronization with the clock signal, the clock signal or the pulse signal having amplitude smaller than amplitude of the pulse signal outputted from the latch circuit.
According to the above construction, the amplitude of the clock signal can be reduced when there is a need for increasing the amplitude of the output of the latch circuit or the shift register circuit that employs a plurality of latch circuits or when the latch circuit or the shift register circuit does not correctly operate unless the drive voltage is increased to a certain degree or higher. Therefore, the load of the external circuit for generating the clock signal is reduced, thereby allowing the consumption of power to be reduced.
In an embodiment of the present invention, the latch circuit further comprises a first circuit having a voltage holding function and a second circuit having a level shifting function, the first and second circuits being constructed so as to own some common elements.
According to the above construction, there is a smaller number of elements and the circuit size is reduced, and this allows the reduction in consumption of power, the improvement of the operating frequency and the reduction in manufacturing cost.
In an embodiment of the present invention, the latch circuit is supplied with a power potential, and an element for controlling the voltage holding function or the level shifting function of the input signal is provided between the power potential and the second circuit.
According to the above construction, the circuit operation can be controlled by controlling the power supply to the second circuit by means of the above element, and this allows the remarkable simplification of the circuit construction for the control and the suppression of consumption of power in the circuit that is not operating.
In an embodiment of the present invention, the latch circuit comprises:
a first p-type transistor and a second p-type transistor, having source electrodes connected to the power potential and gate electrodes connected to drain electrodes of the counterparts;
a first n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor, a drain electrode connected to a ground potential and a gate electrode connected to the drain electrode of the second p-type transistor;
a second n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor, a drain electrode connected to the ground potential and a gate electrode connected to the drain electrode of the first p-type transistor;
a third n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor and a gate electrode that receives the pulse signal as an input;
a fourth n-type transistor having a source electrode connected to the drain electrode of the third n-type transistor, a drain electrode connected to the ground potential and a gate electrode that receives the clock signal as an input;
a fifth n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor and a gate electrode that receives an inverted signal of the pulse signal as an input; and
a sixth n-type transistor having a source electrode connected to the drain electrode of the fifth n-type transistor, a drain electrode connected to the ground potential and a gate electrode that receives the clock signal as an input,
whereby the pulse signal is outputted from the drain electrode of the second p-type transistor, and the inverted signal of the pulse signal is outputted from the drain electrode of the first p-type transistor.
According to the above construction, the latch circuit having the above structure also operates as a normal level shifter circuit that has a function for boosting and outputting the input signal when the clock signal is in the active state and operates as a hold circuit for holding the internal state when the clock signal is in the inactive state. Therefore, this latch circuit operates as a latch circuit having a level shifting function. Accordingly, if the shift register circuit is constructed by combining these circuits, then the amplitude of the clock signal can be made smaller than the amplitude of the pulse signal to be scanned, i.e., the power voltage of the shift register circuit.
Furthermore, the inverted signal of the clock signal is not inputted to this latch circuit, and therefore, the circuit scale is reduced. Furthermore, the load of the clock signal fine is reduced to allow the load of the external circuit to be reduced.
Furthermore, also in this latch circuit, a current flows only when the output signal is inverted instead of the consistent flow of the current when the clock signal level changes, and this provides the merit that almost no increase in consumption of power occurs.
Furthermore, there are only eight transistors that constitute this latch circuit, and therefore, the level shifting function and the latch function can be concurrently achieved with the very small number of-elements.
Furthermore, this latch circuit operates with a delay of one stage of the logic gate at any timing of operation, also with regard to the internal delay, and therefore, the circuit can be operated at very high speed.
In an embodiment of the present invention, the latch circuit comprises:
a first p-type transistor and a second p-type transistor, having source electrodes connected to the power potential and gate electrodes connected to drain electrodes of the counterparts;
a first n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor and a gate electrode connected to the drain electrode of the second p-type transistor;
a seventh n-type transistor having a source electrode connected to the drain electrode of the first n-type transistor, a drain electrode connected to the ground potential and a gate electrode that receives an inverted signal of the clock signal as an input;
a second n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor and a gate electrode connected to the drain electrode of the first p-type transistor;
an eighth n-type transistor having a source electrode connected to the drain electrode of the second n-type transistor, a drain electrode connected to the ground potential and a gate electrode that receives the inverted signal of the clock signal as an input;
a third n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor and a gate electrode that receives the pulse signal as an input;
a fourth n-type transistor having a source electrode connected to the drain electrode of the third n-type transistor, a drain electrode connected to the ground potential and a gate electrode that receives the clock signal as an input;
a fifth n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor and a gate electrode that receives an inverted signal of the pulse signal as an input; and
a sixth n-type transistor having a source electrode connected to the drain electrode of the fifth n-type transistor, a drain electrode connected to the ground potential and a gate electrode that receives the clock signal as an input,
whereby the pulse signal is outputted from the drain electrode of the second p-type transistor, and the inverted signal of the pulse signal is outputted from the drain electrode of the first p-type transistor.
According to the above construction, the latch circuit operates as a normal level shifter circuit that has a function for boosting and outputting the input signal when the clock signal is in the active state and operates as a hold circuit for holding the internal state when the clock signal is in the inactive state. Therefore, this latch circuit operates as a latch circuit having a level shifting function. Accordingly, if the shift register circuit is constructed by combining these circuits, then the amplitude of the clock signal can be made smaller than the amplitude of the pulse signal to be scanned, i.e., the power voltage of the shift register circuit.
Furthermore, the clock signal and its inverted signal are inputted to this latch circuit. The signal path of the hold circuit is completely interrupted when the latch circuit operates as a level shifter circuit, and the signal path of the level shifter circuit is completely interrupted when the latch circuit operates as a hold circuit. Therefore, a stable operation is ensured. That is, the operating margin increases to allow the circuit to be able to cope with a lowered voltage of the input signal and an increase in operating speed.
Furthermore, in this latch circuit, a current flows only when the output signal is inverted instead of the consistent flow of the current when the clock signal level changes, and this provides the merit that almost no increase in consumption of power occurs.
Furthermore, there are only ten transistors that constitute this latch circuit, and therefore, the level shifting function and the latch function can be concurrently achieved with the very small number of elements.
Furthermore, in this latch circuit, there is one current path and the circuit operates with a delay of one stage of the logic gate at any timing of operation, also with regard to the internal delay. Therefore, the circuit can be operated at very high speed.
In an embodiment of the present invention, the latch circuit comprises:
a first p-type transistor and a second p-type transistor, having source electrodes connected to the power potential and gate electrodes connected to drain electrodes of the counterparts;
a first n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor and a gate electrode connected to the drain electrode of the second p-type transistor;
a second n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor and a gate electrode connected to the drain electrode of the first p-type transistor;
a third n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor and a gate electrode that receives the pulse signal as an input;
a fifth n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor and a gate electrode that receives an inverted signal of the pulse signal as an input; and
a ninth n-type transistor having a source electrode connected to the drain electrodes of the third and fifth n-type transistors, a drain electrode connected to the ground potential and a gate electrode that receives the clock signal as an input; and
a tenth n-type transistor having a source electrode connected to the drain electrodes of the first and second n-type transistors, a drain electrode connected to the ground potential and a gate electrode that receives the inverted signal of the clock signal as an input,
whereby the pulse signal is outputted from the drain electrode of the second p-type transistor, and the inverted signal of the pulse signal is outputted from the drain electrode of the first p-type transistor.
According to the above construction, in addition to the aforementioned effects, there are eight constituent transistors in the latch circuit, the number being smaller than in the construction of the aforementioned embodiment. Therefore, a shift register circuit having a very small circuit scale can be constructed.
Furthermore, numbers of inputs of the clock signal and its inverted signal are reduced by half, and this also provides the merit that the capacity of the clock signal line is reduced, thereby allowing the load of the external circuit to be reduced.
In an embodiment of the present invention, the latch circuit comprises:
a first p-type transistor and a second p-type transistor, having source electrodes connected to the power potential and gate electrodes connected to drain electrodes of the counterparts;
a first n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor, a drain electrode connected to a ground potential and a gate electrode connected to the drain electrode of the second p-type transistor;
a second n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor, a drain electrode connected to the ground potential and a gate electrode connected to the drain electrode of the first p-type transistor;
a third n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor and a gate electrode that receives the pulse signal as an input;
a fifth n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor and a gate electrode that receives an inverted signal of the pulse signal as an input; and
a ninth n-type transistor having a source electrode connected to the drain electrodes of the third and fifth n-type transistors, a drain electrode connected to the ground potential and a gate electrode that receives the clock signal as an input,
whereby the pulse signal is outputted from the drain electrode of the second p-type transistor, and the inverted signal of the pulse signal is outputted from the drain electrode of the first p-type transistor.
According to the latch circuit having the above structure, in addition to the aforementioned effects, there are seven constituent transistors, the number being smaller than in the construction of the above embodiment. Therefore, a shift register circuit having a very small circuit scale can be constructed.
Furthermore, numbers of inputs of the clock signal and its inverted signal are reduced by half, and this also provides the merit that the capacity of the clock signal line is reduced, thereby allowing the load of the external circuit to be reduced.
In an embodiment of the present invention, the latch circuit is comprised of first and second logical product and non-disjunction circuits,
the logical product circuit section of the first logical product and non-disjunction circuit receiving the clock signal and the pulse signal as inputs, the non-disjunction circuit section of the first logical product and non-disjunction circuit receiving an output signal of the logical product circuit section and an output signal of the second logical product and non-disjunction circuit as inputs,
the logical product circuit section of the second logical product and non-disjunction circuit receiving the clock signal and the inverted signal of the pulse signal as inputs, and the non-disjunction circuit section of the second logical product and non-disjunction circuit receiving an output signal of the logical product circuit section and an output signal of the first logical product and non-disjunction circuit.
In the above construction, the input signal is taken in only when the clock signal is in the active state, and the internal state is held when the clock signal is in the inactive state. Therefore, this latch circuit operates as a latch circuit having a level shifting function. If the shift register circuit is constructed by combining these circuits, the amplitude of the clock signal can be made smaller than the amplitude of the pulse signal to be scanned, i.e., the power voltage of the shift register circuit.
The logical product and non-disjunction circuit can be constructed as one logic gate, and this allows the reduction in circuit scale.
In an embodiment of the present invention, the logical product and non-disjunction circuit comprises:
a first p-type transistor and a second p-type transistor having source electrodes connected to the power potential and gate electrodes connected to the drain electrodes of the counterparts;
a first n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor, a drain electrode connected to the ground potential and a gate electrode that receives the output signal of the other logical product and non-disjunction circuit as an input;
an eleventh n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor and a gate electrode that receives the inverted signal of the clock signal;
a third n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor and a gate electrode that receives the pulse signal as an input;
a fourth n-type transistor having a source electrode connected to the drain electrode of the third n-type transistor, a drain electrode connected to the ground potential and a gate electrode that receives the clock signal as an input;
a fifth n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor and a gate electrode that receives the inverted signal of the pulse signal as an input; and
a twelfth n-type transistor having a source electrode connected to the drain electrodes of the eleventh and fifth n-type transistors, a drain electrode connected to the ground potential and a gate electrode that receives the inverted signal of the output signal of the other logical product and non-disjunction circuit as an input,
whereby the pulse signal is outputted from the drain electrode of the first p-type transistor, and the inverted signal of the pulse signal is outputted from the drain electrode of the second p-type transistor.
According to the above construction, such a logical product and non-disjunction circuit correctly operates even when the input signal is smaller than the power voltage in the case where the logical product and non-disjunction circuit is applied to a logic circuit (logical product and non-disjunction circuit) having, for example, a shift register function. Therefore, if the shift register circuit is constructed by combining these circuits, the amplitude of the clock signal can be made smaller than the amplitude of the pulse signal to be scanned, i.e., the power voltage of the shift register circuit.
Furthermore, in this logical product and non-disjunction circuit, a current flows only when the output signal is inverted independently of the change in level of the input signal, and this provides the merit that almost no increase in consumption of power occurs.
In an embodiment of the present invention, the latch circuit comprises:
a first non-conjunction circuit that receives the clock signal and the pulse signal as inputs;
a second non-conjunction circuit that receives the clock signal and the inverted signal of the pulse signal as inputs;
a third non-conjunction circuit that receives an output signal of the first non-conjunction circuit and an output signal of a fourth non-conjunction circuit as inputs; and
the fourth non-conjunction circuit that receives an output signal of the second non-conjunction circuit and an output signal of the third non-conjunction circuit as inputs.
According to the above construction, the input signal is taken into the non-conjunction circuit only when the clock signal is in the active state and is not taken in when the clock signal is in the inactive state, so that the internal state is held. Therefore, this latch circuit operates as a latch circuit having a level shifting function. Accordingly, if the shift register circuit is constructed by combining these circuits, the amplitude of the clock signal can be made smaller than the amplitude of the pulse signal to be scanned, i.e., the power voltage of the shift register circuit.
In an embodiment of the present invention, the first and second non-conjunction circuits comprises:
a first p-type transistor and a second p-type transistor, having source electrodes connected to the power potential and gate electrodes connected to the drain electrodes of the counterparts;
a third n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor and a gate electrode that receives the pulse signal as an input;
a fourth n-type transistor having a source electrode connected to the drain electrode of the third n-type transistor, a drain electrode connected to the ground potential and a gate electrode that receives the clock signal as an input;
a thirteenth n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor, a drain electrode connected to the ground potential and a gate electrode that receives the inverted signal of the pulse signal as an input; and
a fourteenth n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor, a drain electrode connected to the ground potential and a gate electrode that receives the inverted signal of the clock signal as an input,
whereby the output signal of the first non-conjunction circuit is outputted from the drain electrode of the first p-type transistor, and the inverted signal of the output signal is outputted from the drain electrode of the second p-type transistor.
According to the above construction, if such a non-conjunction circuit is applied to a logic circuit (non-conjunction circuit) having, for example, a level shifting function, then the circuit correctly operates even when the input signal is smaller than the power voltage. Therefore, if the shift register circuit is constructed by combining this with the normal non-conjunction circuit, then the amplitude of the clock signal can be made smaller than the amplitude of the pulse signal to be scanned, i.e., the power voltage of the shift register circuit.
In an embodiment of the present invention, the latch circuit comprises:
first and second p-type transistors having source electrodes connected to the power potential;
third and fourth p-type transistors having source electrodes connected respectively to the drain electrodes of the first and second p-type transistors, and gate electrodes connected to the clock signal;
third and fifth n-type transistors having source electrodes connected respectively to the drain electrodes of the third and fourth p-type transistors, and gate electrodes connected respectively to an input pulse signal and an inverted signal of the input pulse signal;
fourth and sixth n-type transistors having source electrodes connected respectively to the drain electrodes of the third and fifth n-type transistors, gate electrodes connected to the clock signal, and drain electrodes connected to the ground potential; and
first and second n-type transistors having source electrodes connected respectively to the drain electrodes of the third and fourth p-type transistors, gate electrodes connected respectively to the drain electrodes of the fourth and third p-type transistors, and drain electrodes connected to the ground potential,
whereby the output pulse is outputted from the drain electrode of the fourth p-type transistor, and the inverted signal of the output pulse is outputted from the drain electrode of the third p-type transistor.
According to the above construction, the third and fourth p-type transistors of which the gate electrodes receive the clock signal as the input are incorporated. With this arrangement, the p-type transistors operate so as to limit the current from the power potential side in the operating stage when the output node that outputs the output pulse or its inverted signal comes to have the low level (ground potential), thereby increasing the operating margin.
In an embodiment of the present invention, the latch circuit comprises:
first and second p-type transistors having source electrodes connected to the power potential;
third and fourth p-type transistors having source electrodes connected respectively to the drain electrodes of the first and second p-type transistors, and gate electrodes connected to the clock signal;
third and fifth n-type transistors having source electrodes connected respectively to the drain electrodes of the third and fourth p-type transistors, and gate electrodes connected respectively to an input pulse signal and an inverted signal of the input pulse signal;
fourth and sixth n-type transistors having source electrodes connected respectively to the drain electrodes of the third and fifth n-type transistors, gate electrodes connected to the clock signal, and drain electrodes connected to the ground potential;
first and second n-type transistors having source electrodes connected respectively to the drain electrodes of the third and fourth p-type transistors, and gate electrodes connected respectively to the drain electrodes of the fourth and third p-type transistors; and
seventh and eighth n-type transistors having source electrodes connected respectively to the drain electrodes of the first and second n-type transistors, gate electrodes connected to the inverted signal of the clock signal, and drain electrodes connected to the ground potential,
whereby the output pulse is outputted from the drain electrode of the fourth p-type transistor, and the inverted signal of the output pulse is outputted from the drain electrode of the third p-type transistor.
According to the above construction, the third and fourth p-type transistors of which the gate electrodes receive the clock signal as the input are incorporated. With this arrangement, the p-type transistors operate so as to limit the current from the power potential side in the operating stage when the output node that outputs the output pulse or its inverted signal comes to have the low level (ground potential), thereby increasing the operating margin.
In an embodiment of the present invention, the latch circuit comprises:
first and second p-type transistors having source electrodes connected to the power potential;
third and fourth p-type transistors having source electrodes connected respectively to the drain electrodes of the first and second p-type transistors, and gate electrodes connected to the clock signal;
fifth and sixth p-type transistors having source electrodes connected respectively to the drain electrodes of the first and second p-type transistors, gate electrodes connected respectively to an input pulse signal and an inverted signal of the input pulse signal, and drain electrodes connected respectively to the drain electrodes of the third and fourth p-type transistors;
third and fifth n-type transistors having source electrodes connected respectively to the drain electrodes of the third and fourth p-type transistors, and gate electrodes connected respectively to the input pulse signal and the inverted signal of the input pulse signal;
fourth and sixth n-type transistors having source electrodes connected respectively to the drain electrodes of the third and fifth n-type transistors, gate electrodes connected to the clock signal, and drain electrodes connected to the ground potential; and
first and second n-type transistors having source electrodes connected respectively to the drain electrodes of the third and fourth p-type transistors, gate electrodes connected respectively to the drain electrodes of the fourth and third p-type transistors, and drain electrodes connected to the ground potential;
whereby the output pulse is outputted from the drain electrode of the fourth p-type transistor, and the inverted signal of the output pulse is outputted from the drain electrode of the third p-type transistor.
According to the above construction, the third and fourth p-type transistors of which the gate electrodes receive the clock signal as the input as well as the fifth and sixth p-type transistors of which the gate electrodes receive the input pulse signal and its inverted signal as the inputs are incorporated. With this arrangement, the p-type transistors operate so as to limit the current from the power potential side in the operating stage when the output node that outputs the output pulse or its inverted signal comes to have the low level (ground potential), thereby increasing the operating margin.
In an embodiment of the present invention, the latch circuit comprises:
first and second p-type transistors having source electrodes connected to the power potential;
third and fourth p-type transistors having source electrodes connected respectively to the drain electrodes of the first and second p-type transistors, and gate electrodes connected to the clock signal;
fifth and sixth p-type transistors having source electrodes connected respectively to the drain electrodes of the first and second p-type transistors, gate electrodes connected respectively to an input pulse signal and an inverted signal of the input pulse signal, and drain electrodes connected respectively to the drain electrodes of the third and fourth p-type transistors;
third and fifth n-type transistors having source electrodes connected respectively to the drain electrodes of the third and fourth p-type transistors, and gate electrodes connected respectively to the input pulse signal and the inverted signal of the input pulse signal;
fourth and sixth n-type transistors having source electrodes connected respectively to the drain electrodes of the third and fifth n-type transistors, gate electrodes connected to the clock signal, and drain electrodes connected to the ground potential;
first and second n-type transistors having source electrodes connected respectively to the drain electrodes of the third and fourth p-type transistors, and gate electrodes connected respectively to the drain electrodes of the fourth and third p-type transistors; and
seventh and eighth n-type transistors having source electrodes connected respectively to the drain electrodes of the first and second n-type transistors, gate electrodes connected to an inverted signal of the clock signal, and drain electrodes connected to the ground potential,
whereby the output pulse is outputted from the drain electrode of the fourth p-type transistor, and the inverted signal of the output pulse is outputted from the drain electrode of the third p-type transistor.
According to the above construction, the third and fourth p-type transistors of which the gate electrodes receive the clock signal as the input as well as the fifth and sixth p-type transistors of which the gate electrodes receive the input pulse signal and its inverted signal as the inputs are incorporated. With this arrangement, the p-type transistors operate so as to limit the current from the power potential side in the operating stage when the output node that outputs the output pulse or its inverted signal comes to have the low level (ground potential), thereby increasing the operating margin.
In an embodiment of the present invention, the first, second, third and fifth n-type transistors have a dual-gate structure, and the fourth, sixth, seventh and eighth n-type transistors have a single-gate structure.
According to the above construction, if the transistor located on the ground potential side has the single-gate structure and the transistor located on the output terminal side has the dual-gate structure in the case where the transistor is directly connected between the output terminal of the latch circuit and the ground terminal, then the reduction in the number of elements and the ensuring of the elemental breakdown voltage can be concurrently achieved. In general, with regard to a plurality of transistors connected in series, the higher voltage is applied to the drain side (the higher potential side in the case of the n-type transistor and the lower potential side in the case of the p-type transistor) as compared with the source side (the lower potential side in the case of the n-type transistor and the higher potential side in the case of the p-type transistor). Therefore, it is effective to make the transistor located on the drain side have the dual-gate structure, thereby increasing the elemental breakdown voltage. Since only the relatively low voltage is applied to the source side, the load can be reduced by adopting the single-gate structure, so that the high-speed operation of the shift register circuit and the reduction in the number of elements can be achieved.
In an embodiment of the present invention, the first, second, third and fifth n-type transistors have a channel length longer than the channel length of the fourth, sixth, seventh and eighth n-type transistors.
According to the latch circuit having the above construction, in the case where a plurality of transistors are directly connected between the output terminal of the latch circuit and the ground terminal similar to the above case, the reduction in the number of elements and the ensuring of the elemental breakdown voltage can be concurrently achieved also by making the channel length of the transistor located on the output terminal side longer than the channel length of the transistor located on the ground potential side. As described above, with regard to the plurality of transistors connected in series, the higher voltage is applied to the drain side (the higher potential side in the case of the n-type transistor and the lower potential side in the case of the p-type transistor) as compared with the source side (the lower potential side in the case of the n-type transistor and the higher potential side in the case of the p-type transistor). Therefore, it is effective to make the transistor located on the drain side have the longer channel length, thereby increasing the elemental breakdown voltage. Since only the relatively low voltage is applied to the source side, the load can be reduced by reducing the channel length, so that the high-speed operation of the shift register circuit and the reduction in the number of elements can be achieved.
Also, there is provided a shift register circuit having a plurality of latch circuits for transmitting a pulse signal in synchronization with a clock signal,
the latch circuits each internally having a clock signal input control section for executing control to input and stop the supplied clock signal, and
the clock signal having amplitude smaller than the amplitude of the pulse signal.
According to the above construction, the amplitude of the clock signal is smaller than the amplitude of the pulse signal, i.e., smaller than the power voltage for transmitting the pulse signal. Therefore, the pulse signal having large amplitude can be transmitted without increasing the consumption of power of the external circuit for generating the clock signal. In the above case, the reduction of the load and the reduction in consumption of power of the clock signal line are achieved by stopping the input of the clock signal supplied to each of the latch circuits constructed of the active elements that are required to have a high driving power by means of the clock signal input control section when the latch circuit is inactive.
In am embodiment of the present invention, the clock signal inputted to the latch circuits is only either one of a clock signal of a specified cycle and an antiphase signal of the clock signal.
According to the above construction, the latch circuit operates in synchronization with only either one of the clock signal and its antiphase signal. Therefore, the load of the clock signal line is reduced by half to reduce the consumption of power as compared with the case where both the signals of the clock signal ck and the inverted clock signal /ck are used as in the conventional latch circuits SR shown in FIG. 43.
In an embodiment of the present invention, an output signal of each of the latch circuits is inputted to the latch circuit of the succeeding stage via a first transfer gate and inputted to the latch circuit of the preceding stage via a second transfer gate, and a scanning direction is controlled by selectively making conductive the first or second transfer gate by means of an external signal.
According to the shift register circuit having the above construction, the output signal of each latch circuit is inputted to the latch circuits of the preceding stage and the succeeding stage via the first and second transfer gates, respectively, and the scanning direction of the shift register is controlled by making one of the first and second transfer gates conductive by the external signal.
In the shift register circuit having the above construction, the direction in which the pulse signal propagates can be set in either direction by the input signal to the transfer gate, and therefore, a shift register circuit that can execute scanning in both the directions can be constructed.
In an embodiment of the present invention, an output signal of each of the latch circuits is inputted to the latch circuit of the succeeding stage via a buffer circuit.
In the shift register circuit having the above construction, if there is provided the construction in which, for example, the output pulse signal of the latch circuit is inputted to the latch circuit of the next stage via the buffer circuit, then the driving power with respect to the next stage can be increased by adding the buffer circuit even in the latch circuit with a level shifting function having a relatively small driving power, so that the stable operation and high-speed operation of the shift register circuit can be achieved.
In an embodiment of the present invention, the clock signal input control section is comprised of a first clock signal input control section and a second clock signal input control section, and the latch circuit comprises:
a first p-type transistor and a second p-type transistor having source electrodes connected to a power potential and gate electrodes connected to drain electrodes of the counterparts;
a first n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor, a drain electrode connected to a ground potential and a gate electrode connected to the drain electrode of the second p-type transistor;
a second n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor, a drain electrode connected to the ground potential and a gate electrode connected to the drain electrode of the first p-type transistor;
a third n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor and a gate electrode connected to a pulse signal input node;
a fourth n-type transistor having a source electrode connected to the drain electrode of the third n-type transistor, a drain electrode connected to the ground potential and a gate electrode connected to the first clock signal input control section;
a fifth n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor and a gate electrode connected to an inverted pulse signal input node; and
a sixth n-type transistor having a source electrode connected to the drain electrode of the fifth n-type transistor, a drain electrode connected to the ground potential and a gate electrode connected to the second clock signal input control section,
whereby the drain electrode of the second p-type transistor is made to serve as a pulse signal output node and the drain electrode of the first p-type transistor is made to serve as an inverted pulse signal output node.
According to the above construction, the fourth n-type transistor is turned on when the clock signal inputted from the first clock signal input control section becomes active and the third n-type transistor is turned on when the level of the input pulse signal becomes xe2x80x9cHxe2x80x9d, so that the inverted pulse signal output node comes to have the ground potential. Then, the second p-type transistor is turned on, so that the pulse signal output node comes to have the power potential after a delay behind the trailing edge of the output signal of the inverted pulse signal output node. Therefore, the first p-type transistor is turned off to fix the potential of the inverted pulse signal output node at the ground potential. The fifth n-type transistor is turned off since the input inverted pulse signal is xe2x80x9cLxe2x80x9d, and the second n-type transistor is turned off since the inverted pulse signal output node has the ground potential. Thus, the potential of the pulse signal output node is fixed to the power potential. That is, the above latch circuit operates as a level shifter circuit as a consequence of the output of the pulse signal having the amplitude of the power voltage even though the amplitude of the clock signal is small in the case where the input pulse signal and the output pulse signal have the level xe2x80x9cHxe2x80x9d and the clock signal is active, and the latch circuit operates as a level hold circuit in any other case. Therefore, according to the shift register circuit constructed by serially connecting a plurality of the latch circuits, a pulse signal having greater amplitude is transmitted in synchronization with the clock signal having small amplitude.
Furthermore, the above latch circuit necessitates the clock signal only when this latch circuit is in the active state. Therefore, when the latch circuit is in the inactive state, the reduction of load and the reduction in consumption of power of the clock signal line are achieved by stopping the input of the clock signal by the first and second clock signal input control sections.
Furthermore, the pulse signal from the pulse signal output node rises after a delay behind the trailing edge of the pulse signal from the inverted pulse signal output node. Therefore, the pulse width of the output pulse signal of the pulse signal output node is consistently narrower than the pulse width of the output pulse signal of the inverted pulse signal output node. By using the output pulse signal of the pulse signal output node of each latch circuit, the occurrence of time overlap of the output signals from adjacent latch circuits is eliminated.
In an embodiment of the present invention, the latch circuit comprises:
a first inverter having an input terminal connected to the inverted pulse signal output node; and
a second inverter having an input terminal connected to the pulse signal output node,
whereby the output terminal of the first inverter is made to serve as a new pulse signal output node and the output terminal of the second inverter is made to serve as a new inverted pulse signal output node.
According to the above construction, the pulse signal from the inverted pulse signal output node falls after a delay behind the leading edge of the pulse signal from the pulse signal output node. Therefore, the pulse width of the output pulse signal of the inverted pulse signal output node is consistently narrower than the pulse width of the output pulse signal of the pulse signal output node. By using the output pulse signal of the inverted pulse signal output node of each latch circuit, the occurrence of time overlap of the output signals from adjacent latch circuits is eliminated.
Furthermore, the dull edges of the output pulse signal and the output inverted pulse signal due to the operating delay of the transistors constituting the latch circuits are compensated by the buffering operation (amplifying operation) of the inverter. Particularly, in the present shift register circuit constructed of the multistage latch circuits, the signal compensation is effected immediately behind or immediately before the latch circuit of each stage, and therefore, the occurrence of summation of the signal delays of the latch circuits can be prevented. Therefore, a stable operation can be achieved even with the series of multi-stage latch circuits.
In an embodiment of the present invention, the first clock signal input control section is comprised of a switching means for electrically disconnecting the gate electrode of the fourth n-type transistor from the clock signal input node when the latch circuit becomes inactive and a potential fixing means for fixing the potential of the gate electrode of the fourth n-type transistor that is electrically disconnected from the clock signal input node at a specified potential, and
the second clock signal input control section is comprised of a switching means for electrically disconnecting the gate electrode of the sixth n-type transistor from the clock signal input node when the latch circuit becomes inactive and a potential fixing means for fixing the potential of the gate electrode of the sixth n-type transistor that is electrically disconnected from the clock signal input node at a specified potential.
According to the above construction, if there is effected electrical disconnection between the gate electrodes of the fourth and sixth n-type transistors and the clock signal input node by the switching means of the first and second clock signal input control sections, the potentials of the gate electrodes of the fourth and sixth n-type transistors are fixed to a specified value by the potential fixing means. Thus, the erroneous operation that may occur during the period of transition from the active state into the inactive state of the latch circuit is prevented.
In an embodiment of the present invention, the switching means of the first clock signal input control section is comprised of a fifteenth n-type transistor having a source electrode connected to the clock signal input node, a drain electrode connected to the gate electrode of the fourth n-type transistor and a gate electrode connected to the pulse signal input node, and
the switching means of the second clock signal input control section is comprised of a sixteenth n-type transistor having a source electrode connected to the clock signal input node, a drain electrode connected to the gate electrode of the sixth n-type transistor and a gate electrode connected to the pulse signal output node.
According to the above construction, the fifteenth and sixteenth n-type transistors are turned off when the pulse signal inputted to the gate electrodes of the fifteenth and sixteenth n-type transistors is xe2x80x9cLxe2x80x9d, or when the latch circuit is in the inactive state, thereby stopping the input of the clock signal into the gate electrodes of the fourth and sixth n-type transistors. Thus, the latch circuit operation shifts into the operation as a level hold circuit.
In an embodiment of the present invention, the potential fixing means of the first clock signal input control section is comprised of a seventeenth n-type transistor having a source electrode connected to the gate electrode of the fourth n-type transistor, a drain electrode connected to the ground potential and a gate electrode connected to the power potential, and
the potential fixing means of the second clock signal input control section is comprised of an eighteenth n-type transistor having a source electrode connected to the gate electrode of the sixth n-type transistor, a drain electrode connected to the ground potential and a gate electrode connected to the power potential.
According to the above construction, the gate electrodes of the fourth and sixth n-type transistors are fixed to the ground potential when the gate electrodes of the fourth and sixth n-type transistors and the clock signal input node are electrically disconnected from each other by the switching means. Thus, the erroneous operation that may occur during the period of transition from the active state into the inactive state of the latch circuit is prevented. Furthermore, by constituting the potential fixing means by a transistor, the elemental area becomes smaller than when the means is constructed of a resistor.
In an embodiment of the present invention, the potential fixing means of the first clock signal input control section is comprised of a nineteenth n-type transistor having a source electrode connected to the gate electrode of the fourth n-type transistor, a drain electrode connected to the ground potential and a gate electrode connected to its own source electrode, and
the potential fixing means of the second clock signal input control section is comprised of a twentieth n-type transistor having a source electrode connected to the gate electrode of the sixth n-type transistor, a drain electrode connected to the ground potential and a gate electrode connected to its own source electrode.
According to the above construction, the gate electrodes of the fourth and sixth n-type transistors are fixed to the threshold voltages of the nineteenth and twentieth n-type transistors when the gate electrodes of the fourth and sixth n-type transistors and the clock signal input node are electrically disconnected from each other by the switching means. Thus, the erroneous operation that may occur during the period of transition from the inactive state into the active state of the latch circuit is prevented. Furthermore, the wiring on the circuit is simplified and the circuit area is reduced as compared with the case of the preveous embodiment in which the gate electrodes of the nineteenth and twentieth n-type transistors are connected to the power potential.
In an embodiment of the present invention, the potential fixing means of the first clock signal input control section is comprised of a first resistor provided between the gate electrode of the fourth n-type transistor and the ground potential, and
the potential fixing means of the second clock signal input control section is comprised of a second resistor provided between the gate electrode of the sixth n-type transistor and the ground potential.
According to the above construction, the gate electrodes of the fourth and sixth n-type transistors are fixed to the ground potential when the gate electrodes of the fourth and sixth n-type transistors and the clock signal input node are electrically disconnected from each other by the switching means. Thus, the erroneous operation that may occur during the period of transition from the inactive state into the active state of the latch circuit is prevented. Furthermore, the manufacturing process becomes simple since the structure of the potential fixing means is simplified. Furthermore, the circuit area is reduced by the multi-layer arrangement in which the resistor is provided below the wiring.
In an embodiment of the present invention, the potential fixing means of the first clock signal input control section is comprised of a twenty-first n-type transistor having a source electrode connected to the gate electrode of the fourth n-type transistor, a drain electrode connected to the ground potential and a gate electrode connected to the inverted pulse signal input node, and
the potential fixing means of the second clock signal input control section is comprised of a twenty-second n-type transistor having a source electrode connected to the gate electrode of the sixth n-type transistor, a drain electrode connected to the ground potential and a gate electrode connected to the inverted pulse signal output node.
According to the above construction, the gate electrodes of the fourth and sixth n-type transistors are fixed to the ground potential when the gate electrodes of the fourth and sixth n-type transistors and the clock signal input node are electrically disconnected from each other by the switching means. Thus, the erroneous operation that may occur during the period of transition from the inactive state into the active state of the latch circuit is prevented. By contrast, when the gate electrodes of the fourth and sixth n-type transistors and the clock signal input node are electrically connected to each other by the switching means, the twenty-first and twenty-second n-type transistors are turned off to prevent the conducting current from the gate electrodes of the fourth and sixth n-type transistors to the ground potential.
Also, there is provided an active matrix type image display device comprising: a plurality of data signal lines arranged in a direction of column; a plurality of scanning signal lines arranged in a direction of row; a plurality of pixels that are arranged in a matrix form while being placed in positions surrounded by the data signal lines and the scanning signal lines; a data signal line drive circuit for supplying a video signal to the data signal lines; and a scanning signal line drive circuit for supplying a scanning signal to the scanning signal lines,
at least one of the data signal line drive circuit and the scanning signal line drive circuit being comprised of the shift register circuit claimed in any one of claims 18 through 29.
According to the above construction, either one of the data signal line drive circuit and the scanning signal line drive circuit is constructed of the shift register circuit according to any one of the eighteenth through twenty-ninth aspects of the invention. Therefore, the one signal line drive circuit is driven by the clock signal that has amplitude smaller than the amplitude of the transfer pulse signal (i.e., the power voltage). With this arrangement, the consumption of power of the clock wiring that has a large wiring load capacity due to the long wiring length and the consumption of power of the external circuit for generating the clock are remarkably reduced. Furthermore, when the latch circuit that constitutes the shift register circuit of the signal line drive circuit is in the inactive state, the input of the clock signal into the shift register circuit is stopped by the clock signal input control section, so that the load of the clock signal line is reduced.
In an embodiment of the present invention, one of the signal line drive circuits is comprised of the shift register circuit claimed in claim 22 and
constructed so as to generate a drive signal for driving the corresponding signal line by means of an output signal that has a narrower pulse width out of the two output signals of the pulse signal and the inverted pulse signal from each latch circuit constituting the shift register circuit.
According to the above construction, by generating the drive signal by means of the output signal having the narrower pulse width out of the output pulse signal and the output inverted pulse signal, the occurrence of time overlap of the output signals from the adjacent latch circuits is eliminated. Therefore, in the case where the one signal line drive circuit is the data signal line drive circuit, the sampling signals generated by the adjacent latch circuits do not overlap each other in terms of time. Accordingly, there is no occurrence of the start of writing the video signal into the other data signal line while a video signal is being written into a certain data signal line. In the case of the scanning signal line drive circuit, the scanning signals generated by the adjacent latch circuits do not overlap each other in terms of time. Accordingly, there is no occurrence of the start of writing of the video data into the pixels of the other row while video data are being written into the pixels of a certain row. That is, no noise is superimposed on the video signal in either case of the signal line drive circuits, so that a satisfactory image can be obtained without additionally incorporating any circuit for narrowing the pulse width of the drive signal.
In general, a large through current flows through the level shifter circuit at the time of change of a signal in the above case. However, in the construction of this latch circuit, the through current flows only at the time of change of the output signal (i.e., when the pulse signal is propagating), not at the time of change of the clock signal. Therefore, the consumption of power becomes extremely small.
In an embodiment of the present invention, the image display device comprises:
a level shifter circuit that amplifies the amplitude of a start signal having the same amplitude as that of the clock signal and supplies the resulting signal as the pulse signal to the latch circuit of the first stage in the shift register circuit of the one signal line drive circuit.
According to the above construction, in the one signal line drive circuit, the start signal is inputted to the latch circuit of the first stage of the shift register circuit after being preliminarily boosted. Therefore, even though the latch circuit of the first stage is made to have quite the same construction as that of the latch circuit of the other stage, a stable operation is achieved. Furthermore, the amplitude of the start signal can be made smaller than that of the drive voltage similar to the case of the clock signal, so that the consumption of power of the external circuit for generating the start signal can be reduced.
In an embodiment of the present invention, an image display device comprises:
a level shifter circuit that amplifies the amplitude of a control signal having the same amplitude as that of the clock signal and supplies the resulting signal to the one signal line drive circuit.
According to the above construction, the control signal is inputted to the buffer circuit and so on other than the shift register circuit after being preliminarily boosted. Therefore, the amplitude of all the control signals inputted to the one signal line drive circuit can be made smaller than that of the drive voltage, so that the consumption of power of the external circuit for generating the control signal can be reduced.
In an embodiment of the present invention, the one signal line drive circuit is formed on a substrate identical to that of the pixels.
According to the above construction, the pixels for performing display and the one signal line drive circuit for driving the pixels are fabricated on an identical substrate through identical processes. Thus, the reduction in manufacturing cost and mounting cost and the increase in yield of the mounted products are achieved.
In an embodiment of the present invention, an active element that constitutes each of the one signal line drive circuit and the pixels is a polysilicon thin-film transistor.
According to the above construction, by employing the polysilicon thin-film transistor that has an extremely high driving power as compared with the amorphous silicon thin-film transistor employed in the conventional active matrix type liquid crystal display device, the pixels and the signal line drive circuits are easily formed on the identical substrate.
Furthermore, the polysilicon thin-film transistor has a driving power that is one or two orders of magnitude smaller than the monocrystal silicon transistor although the driving power is much higher than that of the amorphous silicon thin-film transistor. Therefore, if the level shifter circuit is constructed of the polysilicon thin-film transistor, then there is a concern about a significant change in duty ratio of the signal. However, according to the structure of the shift register circuit in the one signal line drive circuit, output signals of an approximately same pulse width can be obtained from the latch circuit of any stage of the shift register circuit, and satisfactory image display is achieved. In the above case, the polysilicon thin-film transistor becomes a large load of the clock signal line since a large channel width must be provided due to its low driving power. However, according to the construction of the shift register circuit of the one signal line drive circuit, the clock signal line is connected to only the driving transistor of the latch circuit in the operating state by the first and second clock signal input control sections, so that the reduction of load of the clock signal line and the reduction in consumption of power of the drive circuit can be achieved.
In an embodiment of the present invention, the polysilicon thin-film transistor is formed on a glass substrate through a process at a temperature of not higher than 600xc2x0 C.
According to the above construction, the polysilicon thin-film transistor is formed on the glass substrate through the processes at the temperature of not higher than 600xc2x0 C. Therefore, the glass that is inexpensive and able to be easily processed to have a large size can be employed as the substrate although the strain point temperature is low, so that a large-size image display device is manufactured at low cost.